1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and in particular to the semiconductor integrated circuit device including an overcurrent limitation circuit having an output voltage that varies according to a variation of a threshold value voltage of an MOS transistor for outputting.
2. Description of Related Art
FIG. 3 shows a circuit diagram illustrating a conventional semiconductor integrated circuit device described in a Patent Document 1 (Japanese Patent Publication Laid-Open No. 2003-197913), which discloses a semiconductor integrated circuit device including an overcurrent limitation circuit.
In FIG. 3, the semiconductor integrated circuit 100 includes an NMOS transistor M1 for outputting formed on a silicon substrate, an overcurrent detection circuit 105 for detecting an overcurrent of the NMOS transistor M1, and an overcurrent limitation circuit 102 that is connected between a gate electrode terminal and a source electrode terminal of the NMOS transistor M1, controls a detected current of the overcurrent detection circuit 105, and has an output voltage that varies according to a variation of a threshold value voltage of the MOS transistor M1. The NMOS transistor M1 connects a gate thereof to an input terminal IN via a resistance element R5 and turns on/off a current of a load 101 whose one end is connected to a power supply VDD according to a control voltage of the input terminal IN.
The overcurrent detection circuit 105 includes resistance elements R3 and R4 that are connected to each other in series for detecting a voltage between a drain terminal and a source terminal of the NMOS transistor M1, and an NMOS transistor M2 for detecting an overcurrent whose gate electrode is connected to a connection point between the resistance elements R3 and R4.
A overcurrent limitation circuit 102 includes a resistance elements R1 and R2 for determining a gate voltage of the NMOS transistor M1 to restrict the overcurrent of the overcurrent detection circuit 105, and an NMOS transistor M3 including a dispersing layer formed in a same process as a base dispersing layer for determining a threshold value voltage of the NMOS transistor M1.
Such an overcurrent limitation circuit 102 functions as a circuit causing a control voltage to vary according to the variation of the threshold value of the NMOS transistor M1. And the overcurrent limitation circuit 102 decreases a variation of a current control value even if the threshold value of the NMOS transistor M1 varies. A gate control voltage Vg of the NMOS transistor M1 when the current is restricted is represented by an expression (1) as below, where Vt denotes a threshold value of the NMOS transistor M3, R1 denotes a resistance value of the resistance element R1, and R2 denotes a resistance value of the resistance element R2.
                                                        Vg              =                                                                    (                                                                  R                        1                                            +                                              R                        2                                                              )                                    /                                      R                    2                                                  ×                Vt                                                                                                                          =                                      (                                          1                      +                                                                        R                          1                                                /                                                  R                          2                                                                                      )                                                  )                            ×              Vt                                                          (        1        )            
As illustrated by the expression (1), the threshold value voltage Vt of the NMOS transistor M3 works together with the gate control voltage Vg of the NMOS transistor M1 when the current is controlled so that a variation of the current limitation value can be decreased.